1. Field of the Invention
The invention pertains to timing circuits such as phase locked loops and delay locked loops.
2. Background of the Invention
Digital circuits generally require timing circuits for generating one or more periodic clock signals. Two common types of timing circuits for establishing a stable clock signal are phase locked loops (PLLs) and delay locked loops (DLLs). PLLs and DLLs are most commonly used to synchronize a local clock signal to an incoming clock signal (e.g., from another, external circuit).
A PLL typically is a negative feedback system that operates by phase locking to an incoming clock signal and creating a duplicate of the incoming clock or a clock signal that is a multiple of the incoming clock signal (e.g., 2×, 4×, 8×, ½×, ¼× of the incoming clock). FIG. 1 is a simplified block diagram showing the basic components of a PLL. In particular, the incoming clock signal fref is placed at one input terminal of a phase detector 103. The other input terminal of the phase detector is coupled to a feedback signal 106 to be described in more detail herein below. The output 108 of the phase detector is a signal (e.g., a voltage or a current) that is a function of the difference in phase between the two input signals. Generally, if the two input signals to phase detector 103 are equal, the output is zero. If the incoming clock signal fref and feedback signal 106 are different in phase, then the phase detector 103 provides output signal 108 that is proportional to the difference of the input signals in both polarity and magnitude. For example, if the phase of the feedback signal 106 is ahead of the phase of the incoming clock signal fref, the phase detector 103 outputs a positive voltage the magnitude of which is proportional to the phase difference. If, on the other hand, the phase of the feedback signal lags the incoming clock signal, then the phase detector outputs a negative voltage, the magnitude of which is proportional to the difference in phase.
The difference signal is passed through a loop filter 107, which generally is a low pass filter that smoothes the difference signal in order to prevent the possibility of the loop becoming unstable for some combinations of high gain at high frequencies and total loop delay beyond some critical value. The output 110 of the loop filter 107 is input to the control terminal of a voltage controlled oscillator (VCO) 101, such as a CMOS ring oscillator, that generates a regular periodic pulse train the frequency of which is a function of the voltage placed at its control input. The output 109 of the VCO 101 may be fed to a frequency multiplier or frequency divider 105 if the VCO frequency range is outside of the frequency range of the incoming clock signal. (Typically, the local oscillator has a frequency range that is multiples higher than the frequency of the incoming clock signal and therefore is divided to generate a signal that is the same frequency as the incoming clock signal with which the PLL is trying to synchronize). The output 109 of the VCO also is the output clock signal of the PLL. It also may be frequency divided or multiplied if the desired output signal is a multiple or divisor of the incoming clock signal. In fact, the several different versions of the output clock signal 109 may be created with the use of one or more frequency dividers or frequency multipliers, if a plurality of clock signals of different frequencies (that are integer multiples of each other) are necessary.
The output of the frequency divider 105 is placed at the second input terminal of the phase detector 103, thus creating a closed loop feedback system in which the circuit will constantly adjust itself to make the two input signals to the phase detector 103 equal in phase, thereby synchronizing the output signal 109 to the incoming clock signal fref. The output of this frequency divider 105 also could be used as a local clock signal if it is at a frequency of interest to the local circuit.
A DLL also is a closed loop negative feedback system that generates an output signal that is synchronized to an incoming clock signal. However, a DLL generally is used to generate a phase delayed version of the incoming signal clock signal (or multiple/divisor thereof). FIG. 2 is a simplified block diagram of a DLL 200. Again, an input clock signal fref is input to the first input terminal of a phase detector 202. The second input of the phase detector 202 is coupled to a feedback signal 203 to be described herein below. The phase detector generates a difference signal 205 that is a function of the difference in phase between its two input signals. This difference signal is input to a loop filter 204 as described above in connection with PLLs. The output 207 of the loop filter 204 is coupled to the control inputs of a plurality of delay elements 2061, 2062, . . . , 206n, coupled in series. The input terminal of the first delay element 2061, receives the incoming reference clock, fref. The output of the last delay element 206n is the feedback signal coupled to the second input terminal of the phase detector 202.
As previously described, the phase detector 205 generates a difference signal proportional (in both polarity and magnitude) to the difference in phase between its two input signals. Accordingly, the DLL also is a negative feedback loop that forces the output of the last delay element to be equal in phase to the incoming clock signal, but delayed exactly one clock cycle of the incoming reference clock signal. By tapping the output of each of the delay elements in the serial chain of delay elements, various phase shifted versions of the incoming reference clock signal are generated. For instance, if there are four delay elements, the output of each delay element will be delayed one quarter of a clock cycle (i.e., 90°) in phase from the preceding delay element. Accordingly, a DLL with four delay elements can generate four clock signals that are synchronized to the incoming reference clock, but phase shifted 90°, 280°, 270° and 360°, respectively. Of course, the 360° shifted signal is the exactly in phase with the incoming reference clock signal (just delayed exactly one clock cycle). Alternately, an inverter can be added anywhere in the chain of delay elements to introduce a 180 phase shift. By doing so, the total delay through the chain will lock at half a clock period rather than a whole clock period. Thus, for example, if there are four delay elements and an inverter in the chain, the delays provided at each tap will be 45°, 90°, 135°, and 180°. This implementation is attractive when all clocks are supposed to have a duty cycle very close to 50%. Although not expressly illustrated for all of the blocks in FIGS. 1 and 2, of course, all of the circuitry in either the exemplary PLL of DLL must be coupled to a power supply in order for the circuit to operate (i.e., be coupled between ground and a power rail). The source of power is illustrated only for the delay elements in FIG. 2 for purposes of example and discussion. Each delay element, of course, is coupled between a supply voltage VDD and ground VSS.
If the power supply fluctuates (i.e., the voltage between VDD and VSS fluctuates), the amount of delay provided by the delay circuits also will fluctuate. Generally, if the voltage on VDD increases, the delay elements will be faster (i.e., will generate a smaller delay) and vice versa. The negative feedback loop of a PLL or DLL will, of course, compensate and readjust timing in response to any such fluctuations, but there will be a temporary jitter in the output(s) of the PLL or DLL. Also, there is a maximum frequency of fluctuations to which a negative feedback loop such as a PLL or DLL can react. If the fluctuations in the power supply (or changes in the incoming reference clock) exceed a certain frequency, the loop cannot react quickly enough, resulting in some instantaneous error. Some time later (depending on the limited speed of the feedback loop) the loop will gradually correct this instantaneous error, until it becomes very small. The maximum speed of a PLL or DLL will largely be dictated by the propagation delay through the circuit elements of the PLL or DLL.
Since accurate timing and synchronization to an external clock typically is critical to the proper operation of digital circuits, great efforts are made to minimize timing jitter, including timing jitter caused by power supply fluctuations. Most efforts to minimize timing jitter caused by power supply fluctuations focus on reducing power supply voltage noise and ripple. Such efforts include the use of precision regulators to regulate the power supply, the use of passive filters to clean up the output of the power supply, and the use of dedicated power supply pads/pins pairs for the timing circuits. Each of these solutions, however, is expensive in one way or another. For instance, regulators require significant circuit area to implement and are power-hungry. Passive filters also require significant circuit area to fabricate. The use of dedicated power supplied pads/pins is expensive and requires a significant amount of circuit area.
Accordingly, it is an object of the present invention to provide an improved timing circuit.
It is another object of the present invention to provide an improved phase locked loop.
It is a further object of the present invention to provide an improved delay locked loop.
It is yet one more object of the present invention to provide a timing circuit with reduced jitter.
It is yet a further object of the present invention to provide a timing circuit with a feed forward cancellation of jitter induced by power supply noise.
It is another object of the present invention to provide timing circuit with reduced sensitivity of jitter to power supply noise.